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    • 专利摘要:
    An electroluminescent device (10) comprising: a substrate (14) at least partially doped with a first conductivity type and having a face (18); light-emitting diodes (LEDs) each comprising at least one undoped or doped three-dimensional semiconductor element (20) of the first type of conductivity and resting on said face; and semiconductor regions (19) forming at least partially doped photodiodes (PH) of a second conductivity type opposite to the first conductivity type and extending in the substrate from said face between at least some of the three-dimensional semiconductor elements, a portion (32) of the first conductivity type substrate extending to said face (18) at each three-dimensional semiconductor element.
    公开号:FR3041153A1
    申请号:FR1558408
    申请日:2015-09-10
    公开日:2017-03-17
    发明作者:Tiphaine Dupont；Erwan Dornel
    申请人:Aledia；
    IPC主号:
    专利说明:

    INTEGRATED LIGHT SENSOR LIGHT EMITTING DEVICE
    Field
    The present invention generally relates to electroluminescent devices based on semiconductor materials and their manufacturing processes. By electroluminescent devices is meant devices adapted to perform the conversion of an electrical signal into an electromagnetic radiation.
    Presentation of the prior art
    For some applications, it is desirable to measure the radiation emitted by a light-emitting device. This is particularly the case for performing tests during the manufacture of the electroluminescent device or when the electroluminescent device is in operation. The measurement of the radiation emitted by an electroluminescent device may be carried out by means of a light sensor, comprising at least one photodiode, distinct from the electroluminescent device, which entails an additional cost. In addition, in order to perform a continuous measurement of the light, the light sensor must generally be placed in the emission field of the light-emitting device and, as a result, block a part of the luminous flux that would be perceived by an observer. which is not desirable.
    It would be desirable to be able to realize the light sensor in an integrated manner with the electroluminescent device. This would easily measure the radiation emitted by the electroluminescent device at desired times, and in particular continuously. The light sensor could, furthermore, be placed so as to directly measure the radiation emitted by the active layers of the electroluminescent device before it is modified by other elements of the electroluminescent device.
    Patent application WO2014 / 154657 discloses an optoelectronic device comprising an integrated light sensor. The optoelectronic device comprises light-emitting diodes in the form of semiconductor nanowires. Some of the wires, normally used to make light-emitting diodes, are modified to form the light sensor.
    A disadvantage of the optoelectronic device described in the patent application WO2014 / 154657 is that the efficiency of the light sensor may be low. In addition, the son used for the light sensor no longer participate in the light emission of the optoelectronic device. The maximum luminous power that can be emitted by such an optoelectronic device is therefore less than that of an optoelectronic device of the same dimensions in which all the semiconductor wires are dedicated to light emission. summary
    Thus, an object of an embodiment is to overcome at least in part the disadvantages of the integrated light sensor electroluminescent devices described above and their manufacturing processes.
    Another object of an embodiment is that the integration of the light sensor with the light emitting device does not result in a decrease in the light power emitted by the light emitting device.
    Another object of an embodiment is that the efficiency of the light sensor is improved.
    Thus, an embodiment provides an electroluminescent device comprising: an at least partially doped substrate of a first conductivity type and comprising a face; electroluminescent diodes each comprising at least one undoped or doped three-dimensional semiconductor element of the first conductivity type and resting on said face; and semiconductor regions forming photodiodes, at least partially doped with a second conductivity type opposite to the first conductivity type and extending in the substrate from said face between at least some of the three-dimensional semiconductor elements, a portion of the substrate of the first conductivity type extending to said face at each three-dimensional semiconductor element.
    According to one embodiment, each three-dimensional semiconductor element is predominantly a compound selected from the group consisting of compounds III-V and compounds II-VI.
    According to one embodiment, the substrate is, at least in part, a semiconductor material selected from the group consisting of silicon, germanium, silicon carbide or GaAs.
    According to one embodiment, the device further comprises conductive tracks on said face in contact with the semiconductor regions.
    According to one embodiment, the device further comprises an at least partially reflective layer covering the semiconductor regions, an insulating layer being interposed between the semiconductor regions and said at least partially reflective layer.
    According to one embodiment, the semiconductor elements are nanowires, microwires and / or pyramidal structures of nanometric or micrometric size.
    According to one embodiment, the device further comprises electrically insulating regions extending along the lateral edges of at least some semiconductor regions.
    According to one embodiment, the device further comprises an insulating layer electrically located at depth in the substrate and comprises, for each semiconductor region, a region of the first type of conductivity interposed between the insulating layer and the semiconductor region.
    According to one embodiment, the semiconductor regions have the form of electrically connected strips or not.
    According to one embodiment, the semiconductor regions are in the form of a hexagonal tiling.
    According to one embodiment, the semiconductor regions form a continuous region traversed by said portions.
    According to one embodiment, the semiconductor regions are formed by ion implantation of dopants.
    According to one embodiment, the semiconductor regions are formed by epitaxy.
    According to one embodiment, the light-emitting diodes are distributed in at least first and second sets of light-emitting diodes ordered separately.
    According to one embodiment, the semiconductor regions are distributed in at least first and second sets of semiconductor regions, the semiconductor regions of the first set of semiconductor regions extending in the substrate from said face between at least some of the three-dimensional semiconductor elements of the semiconductor regions. first set of light-emitting diodes and the semiconductor regions of the second set of semiconductor regions extending in the substrate from said face between at least some of the three-dimensional semiconductor elements of the second set of light-emitting diodes, the semiconductor regions of the first set of semiconductor regions being isolated electrically semiconductor regions of the second set of semiconductor regions.
    Brief description of the drawings
    These and other features and advantages will be set forth in detail in the following description of particular embodiments made without implied limitation in relation to the appended figures in which: FIGS. 1 to 3 are cross-sections, partial and schematic of embodiments of electroluminescent devices with microwires or nanowires; FIGS. 4A-4F are top, partial and schematic views of embodiments of electroluminescent devices illustrating a plurality of regions of the electroluminescent device; Figure 5 is a partial and schematic sectional view of another embodiment of a light-emitting device with microwires or nanowires; FIG. 6 is a partial and schematic section of a structure used for carrying out simulations; and FIG. 7 is an evolution curve of the power absorbed by the light sensor as a function of the radius of the light sensor.
    detailed description
    For the sake of clarity, the same elements have been designated by the same references in the various figures and, moreover, as is customary in the representation of the electronic circuits, the various figures are not drawn to scale. In addition, only the elements useful for understanding the present description have been shown and are described. In particular, the control means of the electroluminescent devices described below are within the reach of those skilled in the art and are not described. In the rest of the description, unless otherwise indicated, the terms "substantially", "about" and "of the order of" mean "to within 10%". Furthermore, in the present description, the term "connected" is used to denote a direct electrical connection, without intermediate electronic component, for example by means of a conductive track, and the term "coupled" or the term "connected", to designate either a direct electrical connection (meaning "connected") or a connection via one or more intermediate components (resistor, capacitor, etc.).
    The present disclosure relates to electroluminescent devices comprising semiconductor elements in the form of microwires, nanowires or pyramids.
    The term "microfil" or "nanowire" denotes a three-dimensional structure of elongated shape, for example cylindrical, conical or frustoconical, in a preferred direction of which at least two dimensions, called minor dimensions, are between 50 nm and 2.5 μm, preferably between 300 nm and 2.5 μm, the third dimension, called the major dimension, being greater than or equal to 1 time, preferably greater than or equal to 5 times and even more preferably greater than or equal to 10 times, the greatest of minor dimensions. In some embodiments, the minor dimensions may be less than or equal to about 1 μm, preferably between 100 nm and 1 μm, more preferably between 300 nm and 800 nm. In some embodiments, the height of each microfil or nanowire may be greater than or equal to 500 nm, preferably between 1 μm and 50 μm.
    In the remainder of the description, the term "wire" is used to mean "microfil or nanowire". Preferably, the average line of the wire which passes through the barycenters of the straight sections, in planes perpendicular to the preferred direction of the wire, is substantially rectilinear and is hereinafter called "axis" of the wire. The base of the wire has, for example, an oval, circular or polygonal shape, in particular triangular, rectangular, square or hexagonal.
    In the remainder of the description, the term pyramid or truncated pyramid designates a three-dimensional structure of pyramidal shape. This pyramidal structure can be truncated, that is to say that the top of the cone is absent, leaving room for a plateau. The base of the pyramid is inscribed in a polygon whose side dimension is from 100 nm to 10 μm, preferably from 1 to 3 μm. The polygon forming the base of the pyramid can be a hexagon. The height of the pyramid between the base of the pyramid and the summit or top plate varies from 100 nm to 20 μm, preferably between 1 μm and 10 μm.
    In the remainder of the description, embodiments will be described in the case of a light emitting diode electroluminescent device.
    FIG. 1 is a partial and schematic cross section of an electroluminescent device 10 made from wires as described previously and adapted to emit electromagnetic radiation.
    The device 10 comprises, from the bottom upwards in FIG. 1: a first polarization electrode 12; a substrate 14, for example a semiconductor, doped with a first type of conductivity, for example doped N-type, and comprising parallel faces 16 and 18, the face 16 being in contact with the electrode 12; semiconductor regions 19 formed in the substrate 14, doped or partially doped with a second conductivity type opposite to the first conductivity type, for example doped P-type, and extending in the substrate 14 from the face 18 over a portion of the thickness of the substrate 14; semiconductor elements 20, which in the present embodiment correspond to wires, three parallel axis wires D being shown, each wire 20 comprising a lower portion 21 of the first conductivity type extending through an upper portion 22 of the first type of conductivity, the lower portion 21 resting on the substrate 14 and possibly being in contact with the substrate 14 or separated from the substrate 14 by a seed portion not shown in FIG. 1; an electrically insulating layer 23 covering the periphery of the lower portion 21 of each wire 20 and covering the face 18 between the wires 20; a shell 25 covering the outer wall 24 of the upper portion 22 of each wire 20, the shell 25 comprising at least one stack of an active layer 26 covering the upper portion 22 and a semiconductor layer 27 of the second type of conductivity covering the active layer 26; a second electrode layer 28 covering each shell 25; and a conductive layer 29, preferably at least partly reflective, for example a metal layer, which can cover the electrode layer 28 between the wires 20 without however extending over the wires 20.
    The electroluminescent device 10 further comprises a third electrode, not shown, in contact with the semiconductor regions 19. The assembly formed by a wire 20 and the shell 25 constitutes an LED. When multiple LEDs LED are formed on the substrate 14, they can be connected in series and / or in parallel and form a set of light emitting diodes. The assembly can include from a few LEDs to a few thousand light emitting diodes LEDs.
    The junction between each P-doped region 19 and the N-type doped portion of the substrate 14, extending around the region 19, forms a photodiode PH.
    The second electrode 28 is connected to a node A1, the first electrode 12 is connected to a node A2 and the third electrode is connected to a node A3. Since the third electrode is not shown in FIG. 1, each semiconductor region 19 is shown connected to the node A3.
    In operation, the voltage applied between the electrodes 12 and 28 is such that each light-emitting diode LED is conducting so that the active layer 26 of each light-emitting diode LED emits light radiation. For each LED, a part of the radiation emitted by the active layer 26 of the LED is led in the wire 20 and escapes into the substrate 14 by the base of the wire 20. This radiation therefore does not participate in the radiation. global light emitted by the electroluminescent device 10 and which is perceived by an observer. FIG. 1 shows diagrammatically examples of paths of such light rays. The inventors have demonstrated that the radiation escaping through the foot of each wire 20 can be picked up, at least partially, by the photodiode PH which surrounds the wire 20. Since the ratio between the light power captured by each photodiode PH and the light power emitted by the neighboring LEDs can be known, the signal supplied by each photodiode PH is therefore representative of the light power emitted by the light emitting diodes adjacent to the photodiode PH.
    According to one embodiment, the photodiodes PH are reverse biased. The inverse current of each photodiode PH then depends on the light radiation captured by the photodiode PH. In the embodiment shown in FIG. 1, this means that the potential at the node A3 and below the potential at the node A2.
    According to another embodiment, the photodiodes PH are forward biased. The photodiodes PH can then be used as a temperature sensor.
    The conductive layer 29 advantageously prevents the PH photodiodes from receiving light radiation through the face 18. The conductive layer 29 improves the homogeneity of the distribution of the current in the electrode layer 28. alternatively, the conductive layer 29 may not be present.
    The substrate 14 may correspond to a one-piece structure or correspond to a layer covering a support made of another material. The substrate 14 is preferably a semiconductor substrate, for example a substrate made of silicon, germanium, silicon carbide or GaAs. Preferably, the substrate 14 is a monocrystalline silicon substrate. Preferably, it is a semiconductor substrate compatible with the manufacturing processes implemented in microelectronics. The substrate 14 may correspond to a multilayer structure of silicon on insulator type, also called SOI (acronym for Silicon On Insulator). The thickness of the substrate 14 is, for example, between 10 μm and 1.5 mm.
    The substrate 14 is doped with the first type of conductivity at least over part of its thickness from the face 18. When the substrate 14 is in one piece, it can be doped uniformly. Alternatively, the substrate 14 may comprise a doped region of the first conductivity type extending from the face 18 in the thickness of the substrate 14, only over a portion of the thickness of the substrate 14, and based on a region less heavily doped or undoped. The substrate 14 is, for example, a doped substrate of the first type of conductivity with a dopant concentration of between 5 * 10 ^^ atoms / cm.sup.2 and 2 * 10.sup.20 atoms / cm.sup.2, preferably between 5 * 10 and 5 * 10 -19 atoms / cm 2, for example about 3 * 10 ^ atoms / cm 2. In the case of a silicon substrate 14, examples of P type dopants are boron (B) or indium (In) and examples of N type dopants are phosphorus (P), arsenic ( As), or antimony (Sb). The face 18 of the silicon substrate 10 may be a face (100) or a face (111).
    Each semiconductor region 19 may have a depth, measured from the face 18, of between 200 nm and 4 μm, preferably between 400 nm and 800 nm. Each region 19 is, for example, doped with the second type of conductivity with a dopant concentration of between 5 * 10 ^^ atoms / cm ^ and 1 * 1q22 atoms / cm ^, preferably between 5 * 1θ1 ^ atoms / cm and 5 * 10l9 atoms / cm 2, e.g. about 6 * 10 ^ - ^ atoms / cm 2. The semiconductor regions 19 do not extend under the wires 20 so that a doped portion 32 of the first conductivity type extends to the face 18 for each wire 20.
    According to one embodiment, each semiconductor region 19 can be formed by ion implantation of dopants. In another embodiment, the semiconductor region 19 may be formed by epitaxy. According to one embodiment, each semiconductor region 19 is produced by at least one implantation step, which can be implemented before the formation of the wires 20 and the shells 25 or after the formation of the wires 20 and the shells 25. preferably, the semiconductor regions 19 are produced by at least one implantation step implemented after the formation of the wires 20 and the shells 25. This makes it possible to prevent dopants from being diffused from the semiconductor regions 19 during the formation stages of the semiconductors 19. LED light emitting diodes. When the semiconductor regions 19 are formed by at least one implantation step carried out after the formation of the wires 20 and the shells 25, the wires 20 and the shells 25 may be covered by a protective dielectric layer.
    According to another embodiment, each semiconductor region 19 can be divided into several undoped or doped semiconductor sub-regions of the second conductivity type, with a concentration of dopants that increases away from the doped substrate 14 of the first conductivity type. . In this case, the semiconductor regions 19 can be made by several implantation steps.
    The first electrode 12 may correspond to a conductive layer which extends on the face 16 of the substrate 14. The material forming the electrode 12 is, for example, nickel silicide (NiSi), aluminum (Al), aluminum silicide (AISi), titanium (Ti), copper (Cu), tungsten silicide (WSig) or titanium silicide (TiSi). Alternatively, the electrode 12 may be made on the side of the face 18 around the region of the substrate 14 where the wires 20 are formed. The third electrode, not shown, may have the same composition as the first electrode 12.
    The insulating layer 23 may be of a dielectric material, for example silicon oxide (SiOg), silicon nitride (SixNy, where x is approximately equal to 3 and y is approximately equal to 4, for example S13N4), silicon oxynitride (in particular of general formula SiOxNy, for example SigONg), hafnium oxide (HfOg) or diamond. For example, the thickness of the insulating layer 23 is between 5 nm and 300 nm, for example equal to about 100 nm. The insulating layer 23 may have a monolayer structure or correspond to a stack of two layers or more than two layers.
    The semiconductor elements 20 are at least partially formed from at least one semiconductor material. The semiconductor material is selected from the group consisting of compounds III-V or compounds II-VI.
    The semiconductor elements 20 may be at least partially formed from semiconductor materials predominantly comprising a III-V compound, for example a III-N compound. Examples of group III elements include gallium (Ga), indium (In) or aluminum (Al). Examples of III-N compounds are GaN, AlN, InN, InGaN, AlGaN or AlInGaN. Other group V elements may also be used, for example, phosphorus or arsenic. In general, the elements in compound III-V can be combined with different mole fractions.
    The semiconductor elements 20 may be, at least in part, formed from semiconductor materials predominantly comprising a II-VI compound. Examples of Group II elements include Group IIA elements, including beryllium (Be) and magnesium (Mg) and Group IIB elements, including zinc (Zn), cadmium (Cd) and mercury ( Hg). Examples of group VI elements include elements of the VIA group, including oxygen (O) and tellurium (Te). Examples of compounds II-VI are ZnO, ZnMgO, CdZnO, CdZnMgO,
    CdHgTe, CdTe or HgTe. In general, the elements in II-VI can be combined with different mole fractions.
    The semiconductor elements 20 may comprise a dopant. By way of example, for compounds III-V, the dopant may be chosen from the group comprising a group II P dopant, for example magnesium (Mg), zinc (Zn), cadmium (Cd ) or mercury (Hg), a group IV P-type dopant, for example carbon (C) or a group IV N-type dopant, for example silicon (Si), germanium (Ge), selenium (Se), sulfur (S), terbium (Tb) or tin (Sn).
    When the three-dimensional semiconductor elements 20 of the optoelectronic device correspond to wires, the total height of each wire may be between 250 nm and 50 μm. Each wire 20 may have an elongate semiconductor structure along an axis substantially perpendicular to the face 18. Each wire 20 may have a generally cylindrical shape, the base of which has, for example, an oval, circular or polygonal shape, in particular triangular, rectangular, square or hexagonal. The axes of two adjacent yarns may be from 0.5 μm to 10 μm and preferably from 1.5 μm to 5 μm. For example, the son 20 may be regularly distributed, in particular according to a hexagonal network.
    According to one embodiment, the lower portion 21 of each wire consists mainly of a compound III-N, for example gallium nitride, doped with a first type of conductivity, for example of N type. The dopant type N can be silicon. The height of the lower portion 21 may be between 200 nm and 25 pm.
    According to one embodiment, the upper portion 22 of each wire is, for example, at least partially made in a compound III-N, for example gallium nitride. The portion 22 may be doped with the first type of conductivity, for example of the N type, or may not be intentionally doped.
    The height of the portion 22 may be between 500 nm and 25 pm. Alternatively, for each wire 20, the insulating layer 23 may extend over a portion of the upper portion 22, not extend over the entire lower portion 21 or extend over a portion of the hull 25. Alternatively, the shell 25 may extend over all or part of the lower portion 21.
    When the three-dimensional semiconductor elements 20 of the optoelectronic device 10 correspond to pyramids, the height of each pyramid may be between 100 nm and 25 μm. Each pyramid may have an elongate semiconductor structure along an axis substantially perpendicular to the face 18. The base of each pyramid may have a general shape of oval, circular or polygonal type, in particular triangular, rectangular, square or hexagonal. The centers of two adjacent pyramids may be from 0.25 μm to 10 μm and preferably from 1.5 μm to 5 μm. By way of example, the pyramids can be regularly distributed, in particular along a hexagonal network.
    In the case of a wire composed mainly of GaN, the crystalline structure of the wire may be of the wurtzite type, the wire extending in the crystallographic direction c.
    The active layer 26 is the layer from which the majority of the radiation supplied by the device 10 is emitted. The active layer 26 may comprise means of confinement. By way of example, the layer 26 may comprise a single quantum well. It then comprises a semiconductor material different from the semiconductor material forming the upper portion 22 and the layer 27 and having a lower band gap than the material forming the upper portion 22 and the layer 27. The active layer 26 may comprise multiple quantum wells. It then comprises a stack of semiconductor layers forming an alternation of quantum wells and barrier layers.
    The semiconductor layer 27 may comprise a stack of several layers comprising in particular: an intermediate layer of conductivity type opposite to the upper portion 22 and covering the active layer 26; and - a bonding layer covering the intermediate layer and covered by the electrode 28.
    The intermediate layer, for example doped P-type, may correspond to a semiconductor layer or a stack of semiconductor layers and allows the formation of a PN or PIN junction, the active layer 26 being between the intermediate layer of type P and the N-type portion 22 of the wire 20 of the PN or PIN junction.
    The bonding layer may correspond to a semiconductor layer or a stack of semiconductor layers and allows the formation of an ohmic contact between the intermediate layer and the electrode 28. For example, the bonding layer may be doped very thinly. strongly of the type opposite to the lower portion 36, until degenerate or semiconductor layers, for example doped P type at a concentration greater than or equal to 10 ^ 0 atoms / cm ^. The stack of semiconductor layers may comprise an electron-blocking layer formed of a ternary alloy, for example gallium aluminum nitride (AlGaN) or indium aluminum nitride (AlInN) in contact with each other. with the active layer and the intermediate layer, to ensure good confinement of the electric carriers in the active layer.
    The second electrode 28 is adapted to polarize the active layer 26 covering each wire 20 and to let the electromagnetic radiation emitted by the LEDs LED. The material forming the electrode 28 may be a transparent and conductive material such as indium tin oxide (ITO), zinc oxide which may or may not be doped with aluminum. or gallium, or graphene. By way of example, the electrode layer 28 has a thickness of between 5 nm and 200 nm, preferably between 20 nm and 50 nm.
    An example of a method for manufacturing LEDs is described in patent application US2014 / 0077151.
    According to another embodiment, each semiconductor element 20 is not in direct contact with the substrate 14 but rests on a portion of a material promoting the growth of the semiconductor elements 20, called seed pads. For example, the material constituting the seed pads can be a nitride, a carbide or a boride of a transition metal of column IV, V or VI of the periodic table of the elements or a combination of these compounds. By way of example, the seed spots may be aluminum nitride (AlN), aluminum oxide (Al 2 O 3), boron (B), boron nitride (BN), titanium (Ti), of titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), hafnium (Hf), hafnium nitride (HfN), niobium (Nb), niobium nitride (NbN) , of zirconium (Zr), zirconium borate (ZrBg), zirconium nitride (ZrN), silicon carbide (SiC), nitride and tantalum carbide (TaCN), or magnesium nitride in the form MgxNy where x is about 3 and y is about 2, for example magnesium nitride in the form MggNg. The seed pads may be doped with the same type of conductivity as the substrate 14. The seed pads have, for example, a thickness of between 1 nm and 100 nm, preferably between 10 nm and 30 nm.
    When the seed pads are aluminum nitride, they can be substantially textured and have a preferred polarity. The texturing of the seed pads can be obtained by an additional treatment carried out after the deposition of the seed layer. This is, for example, annealing under an ammonia (NH 3) stream. In the case of a wire composed mainly of GaN, each seedpot can promote the growth of GaN with the N polarity.
    FIG. 2 shows another embodiment of a light-emitting device 40. The light-emitting device 40 comprises all the elements of the light-emitting device 10 shown in FIG. 1 and further comprises electrically insulating regions 42 extending into the light-emitting device 40. substrate 14 from the face 18 and laterally surrounding the semiconductor regions 19. The insulating regions 42 are, for example, silicon oxide. Each insulating region 42 preferably has a depth greater than or equal to the depth of the semiconductor region 19 surrounding it. The insulating regions 42 make it possible to reduce the leakage currents in each photodiode PH due to the polarization of the LEDs. In addition, the insulating regions 42 make it possible to reduce the diffusion of dopants from the semiconductor regions 19 to the portion 32. The insulating regions 42 are, for example, obtained by a method of forming shallow trench isolation structures or ITS structures. (acronym for Shallow Trench Insulation).
    In FIG. 2, germination pads 44 have also been represented under each wire 20.
    FIG. 3 represents another embodiment of an electroluminescent device 50. The electroluminescent device 50 comprises all the elements of the light-emitting device 40 represented in FIG. 2 and further comprises an electrically insulating layer 52, located deep within the substrate 14, and delimiting with the insulating regions 42, for each semiconductor region 19, a region 54 of the doped substrate 14 of the first conductivity type and electrically isolated from the rest of the substrate 14. Each region 54 of the first conductivity type is interposed between one of the semiconductor regions 19 and the insulating layer 52. Each region 54 of the first conductivity type is, moreover, preferably surrounded by the insulating region 42 which surrounds the semiconductor region 19. The insulating layer 52 is, for example, for example, silicon oxide. Each photodiode is formed by the junction between the semiconductor region 19 and the underlying region 54. Each region 54 is connected to a node A4 (not shown). The insulating layer 52 delimits, in addition, the regions 56 of the substrate 14 doped with the first type of conductivity on which the wires 20 rest. Each region 56 is connected to the node A2. The node A4 can be electrically connected to the node A2. In this case, the node A4 and the node A2 are at the same electrical potential. The substrate 14 corresponds, for example, to an SOI structure. The electroluminescent device 50 has parasitic currents at the level of the photodiodes which are reduced compared with the electroluminescent device 40.
    FIGS. 4A to 4F show top, partial and schematic views of the face 18 of the electroluminescent device 10 and conductive pads 57 corresponding to the third electrode A3 described above. In FIGS. 4A to 4F, the area 58 of the face 18 of the substrate 14 on which the wires 20, not shown, is delimited by a dashed line.
    As shown in these figures, the conductive pads 57 are preferably located outside the zone 58 of the face 18 of the substrate 14 on which the light-emitting diodes are located. The semiconductor regions 19 may have any shape, for example the form of rectilinear and parallel strips completely traversing the zone 58, as represented in FIGS. 4A and 4B, of rectilinear and parallel strips traversing only partially the zone 58, as this 4C and 4F, or rectilinear strips which intersect as shown in FIG. 4E and which delimit hexagonal openings 59, each hexagonal opening 59 being located at a semiconductor element 20. The semiconductor regions are shown in FIGS. 19 may be distinct, as shown in Figures 4A, 4B, 4C and 4F, or be connected to each other as shown in Figures 4D and 4E. Each conductive pad 57 may be connected to all the semiconductor regions 19, as shown in Figures 4A, 4D and 4E or only to some of them, as shown in Figures 4B, 4C and 4F. As shown in FIG. 4F, the zone 58 can be divided into several subregions PIX1, PIX2, PIX3 and PIX4, each conductive pad 57 being connected to the semiconductor regions 19 associated only with one of these PIX1 subregions, PIX2, PIX3 and PIX4. Such a configuration makes it possible in particular to process separately the signals provided by the photodiodes associated with each subregion PIX1, PIX2, PIX3 and PIX4. The portions of the substrate 14 associated with each pixel PIX1, PIX2, PIX3 and PIX4 may be electrically insulated from each other so that the light-emitting diodes of one of the pixels PIX1, PIX2, PIX3 and PIX4 may be controlled independently of the light-emitting diodes. another pixel PIX1, PIX2, PIX3 and PIX4. In Figs. 4A-4F, the semiconductor regions 19 are shown in the form of bands. Alternatively, the semiconductor regions 19 may correspond, in top view, to a plane extending over all or part of the zone 58 and traversed by openings, each opening being located at a semiconductor element 20.
    FIG. 5 represents another embodiment of an electroluminescent device 60. The electroluminescent device 60 comprises all the elements of the light-emitting device 10 represented in FIG. 1 and further comprises conductive tracks 62, for example metallic, covering the semiconductor regions 19 and in contact with the semiconductor regions 19. The conductive tracks 62 are connected to the conductive pads 57, not shown in FIG. 5. The conductive tracks 62 improve the current conduction of the semiconductor regions 19 towards the conductive pads 57. in the case where seed pads 44 made of a conductive material are present, the conductive tracks 62 may be of the same material as the seed pads 44 and may be produced simultaneously with the seed pads 44.
    FIG. 6 represents, in a partial and schematic manner, a simplified structure of the LED that has been used to determine by simulation the evolution of the light power absorbed by the photodiode PH when the dimensions of the photodiode PH vary. The LED is represented by the wire 20 and the semiconductor layer 27. The light emission is carried out at the interface between the wire 20 and the layer 27. For the simulations, the photodiode PH has been represented by a zone of depletion 64, also called space charge area, which is formed in operation at the junction between the P type conductivity semiconductor region 19 and the rest of the N type substrate 14. For the simulations, the semiconductor region 19 surrounds the N-type portion 32 of the substrate 14 under the wire 20 which extends to the wire 20. We call e the thickness of the depletion zone 64, P the depth of the semiconductor region 19 and R the mean radius, between the axis D and the internal lateral edge of the depletion zone 64, that is to say the mean radius of the portion 32. The portion 32 may have a cross section, perpendicular to the axis D, having the shape of a circle. In this case, the radius R corresponds to the radius of the portion 32. The portion 32 may have a cross section having the shape of a polygon. In this case, the average radius R corresponds to the mean of the distance between the axis D and the lateral edge of the portion 32.
    FIG. 7 represents two points P1 and P2 and a curve C, obtained by simulation from the structure of FIG. 6, of evolution of the absorbed light power Paps by the photodiode PH as a function of the radius R. For the simulations, the average radius of the yarn was 0.7 μm and the depth P was 500 nm. The point P1 was obtained for a thickness e of the depletion zone 64 equal to 100 nm. The point P2 was obtained for a thickness e of the depletion zone 64 equal to 300 nm. Curve C was obtained for a thickness e of the depletion zone 64 equal to 200 nm. The absorbed light power Paps is maximum when the average radius R is substantially equal to the average radius of the wire 20. In addition, the absorbed light power Paps increases as the thickness e of the depletion zone 64 increases. However, a compromise must be found between the thickness e of the depletion zone 64 and the dimensions of the semiconductor region 19 which must be sufficient to obtain a suitable conduction of the current detected by the photodiode PH.
    For a current injected into the LED of about 10 μΑ and an external quantum efficiency of the active layer 26 of about 80%, the maximum power absorbed Paps is of the order of 2% to 3% and the current supplied by the photodiode is about 0.2 μΑ. The intensity of this current is compatible with the devices conventionally used for processing the signals provided by sensors.
    Particular embodiments have been described. Various variations and modifications will be apparent to those skilled in the art. In particular, although in the previously described embodiments the semiconductor regions 19 are P-type doped and the substrate 14 and the wires 20 are at least partly N-doped, it is clear that the conductivity types can to be reversed.
    权利要求:
    Claims (15)
    [1" id="c-fr-0001]
    An electroluminescent device (10; 40; 50; 60) comprising: a substrate (14) at least partially doped with a first conductivity type and comprising a face (18); light-emitting diodes (LEDs) each comprising at least one undoped or doped three-dimensional semiconductor element (20) of the first type of conductivity and resting on said face; and semiconductor regions (19) forming at least partially doped photodiodes (PH) of a second conductivity type opposite to the first conductivity type and extending in the substrate from said face between at least some of the three-dimensional semiconductor elements, a portion (32) of the first conductivity type substrate extending to said face (18) at each three-dimensional semiconductor element.
    [2" id="c-fr-0002]
    An electroluminescent device according to claim 1, wherein each three-dimensional semiconductor element (20) is predominantly of a compound selected from the group consisting of III-V compounds and II-VI compounds.
    [3" id="c-fr-0003]
    Electroluminescent device according to claim 1 or 2, wherein the substrate (14) is, at least in part, a semiconductor material selected from the group consisting of silicon, germanium, silicon carbide or GaAs.
    [4" id="c-fr-0004]
    The electroluminescent device according to any one of claims 1 to 3, further comprising conductive tracks (62) on said face (18) in contact with the semiconductor regions (19).
    [5" id="c-fr-0005]
    Electroluminescent device according to any one of claims 1 to 4, further comprising an at least partially reflective layer (29) covering the semiconductor regions (19), an insulating layer (23) being interposed between the semiconductor regions ( 19) and said at least partially reflective layer.
    [6" id="c-fr-0006]
    Electroluminescent device according to any one of claims 1 to 5, wherein the semiconductor elements (20) are nanowires, microwires and / or pyramidal structures of nanometric or micron size.
    [7" id="c-fr-0007]
    The electroluminescent device according to any one of claims 1 to 6, further comprising electrically insulating regions (42) extending along the side edges of at least some semiconductor regions (19).
    [8" id="c-fr-0008]
    An electroluminescent device according to any one of claims 1 to 7, further comprising an electrically insulating layer (52) located deep within the substrate (14) and comprising, for each semiconductor region (19), a region ( 54) of the first type of conductivity interposed between the insulating layer (52) and the semiconductor region (19).
    [9" id="c-fr-0009]
    9. Electroluminescent device according to any one of claims 1 to 8, wherein the semiconductor regions (19) have the form of bands electrically connected or not.
    [10" id="c-fr-0010]
    An electroluminescent device according to any one of claims 1 to 8, wherein the semiconductor regions (19) are in the form of hexagonal tiling.
    [11" id="c-fr-0011]
    An electroluminescent device according to any one of claims 1 to 8, wherein the semiconductor regions (19) form a continuous region traversed by said portions (32).
    [12" id="c-fr-0012]
    An electroluminescent device according to any one of claims 1 to 11, wherein the semiconductor regions (19) are formed by ion implantation of dopants.
    [13" id="c-fr-0013]
    An electroluminescent device according to any one of claims 1 to 11, wherein the semiconductor regions (19) are formed by epitaxy.
    [14" id="c-fr-0014]
    The electroluminescent device according to any one of claims 1 to 11, wherein the light emitting diodes (LEDs) are distributed into at least first and second sets of light-emitting diodes separately controlled.
    [15" id="c-fr-0015]
    The electroluminescent device according to claim 14, wherein the semiconductor regions (19) are divided into at least first and second sets of semiconductor regions (19), the semiconductor regions of the first set of semiconductor regions extending in the substrate from said face between at least some of the three-dimensional semiconductor elements of the first set of light-emitting diodes and the semiconductor regions of the second set of semiconductor regions extending in the substrate from said face between at least some of the three-dimensional semiconductor elements of the second set of light-emitting diodes, the semiconductor regions of the first set of semiconductor regions being electrically isolated from the semiconductor regions of the second set of semiconductor regions.
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    同族专利:
    公开号 | 公开日
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    FR3076078B1|2017-12-27|2021-11-26|Aledia|OPTOELECTRONIC DEVICE WITH THREE-DIMENSIONAL DIODE MATRIX|
    FR3077653A1|2018-02-06|2019-08-09|Aledia|OPTOELECTRONIC DEVICE WITH ELECTRONIC COMPONENTS AT THE REAR-SIDE OF THE SUBSTRATE AND METHOD OF MANUFACTURE|
    FR3096509B1|2019-05-20|2021-05-28|Aledia|OPTOELECTRONIC DEVICE WITH ELECTROLUMINESCENT DIODES OF WHICH A DOPED ZONE INTEGRATS AN EXTERNAL PORTION BASED ON ALUMINUM AND GALUM NITRIDE|
    法律状态:
    2016-09-20| PLFP| Fee payment|Year of fee payment: 2 |
    2017-03-17| PLSC| Search report ready|Effective date: 20170317 |
    2017-09-21| PLFP| Fee payment|Year of fee payment: 3 |
    2018-09-21| PLFP| Fee payment|Year of fee payment: 4 |
    2019-09-20| PLFP| Fee payment|Year of fee payment: 5 |
    2021-06-11| ST| Notification of lapse|Effective date: 20210506 |
    优先权:
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    FR1558408A|FR3041153B1|2015-09-10|2015-09-10|LIGHT EMITTING DEVICE WITH INTEGRATED LIGHT SENSOR|FR1558408A| FR3041153B1|2015-09-10|2015-09-10|LIGHT EMITTING DEVICE WITH INTEGRATED LIGHT SENSOR|
    PCT/FR2016/052275| WO2017042512A1|2015-09-10|2016-09-09|Light-emitting device with integrated light sensor|
    US15/758,721| US10418506B2|2015-09-10|2016-09-09|Light-emitting device with integrated light sensor|
    EP16777719.2A| EP3347917B1|2015-09-10|2016-09-09|Electroluminescent device with integrated light sensor|
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